can bit timing calculator

What is CAN bit timing?

CAN bit timing defines how each node on a CAN bus divides a single bit into time segments so every device samples the same data at nearly the same instant. If your timing is poor, nodes may still communicate on a bench, but fail in real wiring, noise, or temperature conditions.

At a high level, one CAN bit is split into:

• Sync Segment (fixed at 1 TQ)
• TSEG1 (propagation + phase segment 1)
• TSEG2 (phase segment 2)

The sample point is typically at the end of TSEG1. For many systems, sample points around 80% to 87.5% are common, but the best value depends on bus length, bitrate, transceivers, and network conditions.

Core formulas used by this calculator

This tool uses the common nominal bit timing model:

Where:

• fCAN is the CAN peripheral clock.
• BRP is the baud-rate prescaler.
• 1 + TSEG1 + TSEG2 is the total time quanta per bit.

Important: some MCUs encode these values as register fields with “minus one” offsets, or use slight implementation differences. Always map calculated values to your specific controller datasheet before deploying.

How to use this CAN bus baud rate calculator

1) Enter the CAN clock

Use the actual clock feeding the CAN peripheral, not necessarily the CPU clock.

2) Enter target bitrate and sample point

Examples: 125 kbps, 250 kbps, 500 kbps, or 1000 kbps (1 Mbps). Sample point defaults to 87.5%, a practical starting point for many classic CAN networks.

3) Set hardware limits

Use your controller’s valid ranges for BRP, TSEG1, TSEG2, and SJW. The defaults are broad and may exceed your MCU’s exact limits.

4) Review candidates

The calculator ranks valid results by bitrate error first, then sample-point error. Pick a setting with low bitrate error, realistic sample point, and proper SJW for your network.

Practical tuning tips

• Keep bitrate error as close to 0% as possible.
• Use higher TQ/bit when available for finer timing resolution.
• For longer buses, a later sample point can improve robustness.
• Set SJW ≤ TSEG2 and within controller limits.
• Validate final settings on real hardware with a scope or CAN analyzer.

Common mistakes when setting CAN timing

Using the wrong clock source

If your peripheral is clocked from a divided PLL and you assume core frequency, all timing math is wrong.

Ignoring register encoding

Many drivers require values like BRP-1 or TSEG1-1. Double-check the API and reference manual.

Assuming CAN FD data phase rules are identical

This page targets nominal classic CAN timing behavior. CAN FD adds data-phase timing constraints and transceiver performance considerations.

Quick reference: typical targets

• 125 kbps: industrial controls, longer buses
• 250 kbps: mixed legacy/modern systems
• 500 kbps: very common automotive and embedded rate
• 1 Mbps: short, well-designed buses with tight timing

Final checklist before deployment

1. Confirm physical-layer design (termination, wiring, stubs).
2. Apply calculated values with correct register offsets.
3. Verify error counters remain stable under worst-case load.
4. Test across temperature and supply variation.
5. Document chosen timing for future maintenance.