rc delay calculator

Calculate delay for a resistor-capacitor network using your threshold crossing point.

Charging delay: t = -RC ln(1 - p) | Discharging delay: t = -RC ln(p)
where p is threshold as a fraction of final voltage (for example, 50% = 0.5).

Resistance (R)

Capacitance (C)

Threshold (%)

What is RC delay?

RC delay is the time response created by a resistor and capacitor in series or in a simple first-order network. When voltage is applied, the capacitor does not change instantly. It charges or discharges exponentially, and that creates a measurable delay before a node reaches a logic threshold.

This matters in digital electronics, analog filters, debounce circuits, pulse shaping, timing networks, and reset lines. Even short PCB traces and input capacitance can create practical RC delay in high-speed systems.

Core formulas

1) Time constant

The fundamental quantity is the time constant: τ = R × C

After one time constant, a charging waveform reaches about 63.2% of its final value. A discharging waveform falls to about 36.8% of its initial value.

2) Delay to threshold

Charging to fraction p of final value: t = -RC ln(1 - p)
Discharging to fraction p of initial value: t = -RC ln(p)

For a 50% threshold, delay is approximately 0.693RC. That is why you often see the rule of thumb t_pd ≈ 0.69RC.

How to use this calculator

Enter resistance value and unit (Ω, kΩ, MΩ).
Enter capacitance value and unit (F to pF).
Enter threshold in percent (for CMOS midpoint, 50% is a common first estimate).
Click Calculate Delay to get τ, rising delay, falling delay, and common timing references.

Worked example

Suppose R = 10 kΩ and C = 100 nF. Then τ = 0.001 s = 1 ms.

50% delay: 0.693τ = 0.693 ms
90% charging time: -τ ln(0.1) = 2.303 ms
10–90% rise time: about 2.2τ = 2.2 ms

This gives you a quick intuition: increasing either R or C scales delay linearly.

Design tips for real circuits

Choose realistic threshold values

Logic inputs are not always exactly 50% of supply voltage. Check your datasheet for V_IL and V_IH, then use those percentages for better timing estimates.

Account for tolerances

Real resistors and capacitors have tolerance (for example, ±1% resistor, ±10% capacitor). Worst-case delay can shift significantly. If timing is critical, analyze min/max combinations.

Watch leakage and input impedance

Input leakage currents, transistor base/gate behavior, and loading can modify effective R and C. In precision timing applications, buffer the node or simulate the full circuit.

Common mistakes

Mixing units (nF vs µF) and getting a 1000× error.
Using 0% or 100% threshold, which is mathematically invalid for ideal exponential crossing time.
Assuming delay is the same in both directions without checking threshold definition.
Ignoring parasitic capacitance from traces, probes, and device pins.

Quick FAQ

Is RC delay linear?

Delay scales linearly with R and C, but the waveform itself is exponential.

Why do rising and falling delays differ?

They are equal only for symmetric threshold choices around the normalized waveform (for example, 50% with ideal 0↔V steps). Different thresholds create different times.

Can I use this for gate delay estimation?

Yes, as a first-order approximation (Elmore-style intuition). For final sign-off in fast designs, use SPICE and actual transistor/interconnect models.